Semiconductor Industry Primer
This Semiconductor Industry Primer will help you understand each of the 5 stages of the leading-edge semiconductor industry's supply chain — and why China has little chance of catching up to the West.
There are 5 stages of the supply chain in the global semiconductor sector. This Semiconductor industry primer will help you get up to speed with each of the 5 stages involved in manufacturing a leading-edge semiconductor chip — and help you understand how it has managed to attain its current status of being a geopolitical chess piece.
The video linked above is a basic primer of the global semiconductor industry. Basically, the semiconductor industry from an outsider’s POV is a huge, sprawling monolith with its own internal universe - that is split into 5 distinct sub-sectors. Each subsector is itself ultra-complex to the layman, almost comparable in scale to the respective subsectors within the O&G industry. To illustrate, you can pretty much treat each semiconductor sub-sector as being equal in depth & complexity as some other entire industries.
As the excellent video above explains, the five broad sub-sectors that the wider Semiconductor industry can be divided into occupy different points in the industry’s value chain. They are:
Instruction Set Architecture (ISA) - e.g. Intel, AMD and ARM
Chip Design - e.g. Apple, Google, Alibaba, Intel, Samsung, etc.
Fabrication - e.g. TSMC, Samsung, Intel
Equipment & Software - e.g. ASML
Packaging & Testing - (highly fragmented)
You might have noticed that there are some companies which represent overlapping subsectors. This is because companies the likes of Intel and Samsung are known as Integrated Device Manufacturers (IDM) - which are basically vertically-integrated semiconductor conglomerates which combine several of the above subsectors into one company. In the interest of brevity, I’m just going to give you a quick overview of each subsector and their respective significance to the wider semiconductor industry.
1) Instruction Set Architecture (ISA)
The Instruction Set Architecture (ISA) is basically the most fundamental “language” that a semiconductor chip “talks” in. There’s actually an even more fundamental “language” called micro-operations (see what I mean?) — but for all practical intents and purposes, this description is mostly correct.
The reason why there is a need for a common semiconductor “language” is the same reason that humans need to speak in a common language - standardization. Given how there are literally millions of software companies around the world, it would be a logistical nightmare for developers to write software if they needed to write a different set of code for each different semiconductor chip. This is why over time, this subsector has aggregated into only 2 dominant ISAs across the entire world today - Complex Instruction Set Computer (CISC) and Reduced Instruction Set Computer (RISC).
The layman’s way to describe the difference between CISC and RISC is like this - CISC can handle very complicated instructions within one instruction “set”; while RISC can only do very simple instructions within one instruction “set”. You can think of “sets” as similar to a workout “rep” - it’s basically how long one line of code that can be processed “in one go” is per instruction set. It’s easy to imagine how CISC can handle more complicated instructions and therefore churn out higher performance per instruction set; while RISC with its shorter instructions sets benefits from more efficient processing and therefore higher power efficiency. This makes CISC more suitable for workstations and laptops where performance is a priority; while RISC tends to be used in mobile devices where battery life is a priority.
If you’re a tech enthusiast, you will by now be familiar with how incredible the performance per watt of the Apple M1 chip which came out last year is. That’s because the Apple M1 chip does some semiconductor magic which combines both the advantages of RISC’s better power efficiency with CISC’s higher performance capacity into one RISC-based chip. It is also why people are saying that the future of this ISA subsector belongs to ARM (i.e. RISC), with Intel’s legacy x86 ISA (i.e. CISC) supposedly rendered obsolete by it. You can read more about this in the article linked below, where I do my best to simplify how the Apple M1 chip actually works:
Now you may be wondering - if Intel’s CISC architecture is about to become obsolete, then how can AEM as an Intel proxy be a good stock? The simple answer is that the quick demise of CISC has been grossly exaggerated. While it’s true that RISC is the future of ISA architectures, there are still plenty of Windows PCs running on x86 or x64 CISC architecture which are not going away anytime soon (and Steam Decks). While a betting man will always bet on the long-term dominance of RISC, it is probably going to take several decades before CISC stops being relevant - simply by virtue of how many existing CISC devices there are. Keep in mind that even if the PC industry isn’t growing, it’s still a titanic industry with an annual TAM of about $150 billion - and you can bet your last dollar that the pandemic has only given the CISC architecture a second lease at life (simply by virtue of how many more grandmas are now learning how to use Zoom on their PCs to attend church).
Anyway, the point to take home is that this ISA subsector really only has 3 players in the entire world - Intel and AMD representing CISC, and ARM representing RISC. Thus, it represents a bottleneck for the entire Semiconductor sector - you either work with them or go home. This is the first reason why the semiconductor sector as a whole can be said to be a “geopolitical chess piece” — all 3 companies are firmly situated in Western economies.
2) Chip Design
Chip Design represents the 2nd subsector of this industry - and here there are many more players than within the ISA subsector. Remember how we talked about Apple designing the M1 chip earlier? That’s because Apple only designed the chip - after which they then outsource the manufacturing to foundries like TSMC.
Since this is just a design stage, companies occupying this stage of the supply chain can get mostly everything done via software. As you can imagine, there are tons and tons of different “sub-sub sectors” within the Chip Design subsector - you need the guy drawing the chip, the guy aligning the design with the use-case, the guy who tests the design for defects before sending it to the manufacturer, etc. And if you imagine harder, you can also visualize that each of these “sub-sub sectors” have their own versions of standardization - e.g. everyone tends to use the same software to draw a chip design, just like how everyone in the finance industry tends to use Excel for modeling work.
The fact that standardization can exist within a “sub-sub sector” just tells you how sprawling this Chip Design subsector is. The video below describes the challenges being faced in the latter semiconductor verification “sub-sub sector” - you can see how complicated it is just to test the finished software design for defects, before shipping it out to the manufacturer:
Since anyone can design a chip using software, it’s not difficult to see why there are quite a few players in this space. As we’ve mentioned, Apple is one such occupant - and its competitors include Google, Amazon, Alibaba, Meta, AMD… the list goes on. Obviously, Intel is also an industry player here as it designs its chips based on the x86 CISC architecture; while Samsung also designs the Exynos chips for use in its Samsung mobile phones. Intel and Samsung get special mention here because they are both IDMs - which we’ll get to in a second.
Of course, this is not to say that the barriers to entry in this subsector are low - you still need a lot of money and a lot of staying power to design a chip with 10 billion transistors that works as intended. Hence, most of the players here are blue-chip companies with household names like Apple or Google. However, since money is no object for a government the likes of Washington or Beijing, it does not serve as a bottleneck to the wider Semiconductor industry and is therefore of lesser strategic importance in the geopolitical games to come.
3) Fabrication
This subsector is the main protagonist of the entire Semiconductor umbrella industry, for one very simple reason - there are only 3 global players where it matters in the entire world. These are TSMC, Samsung and Intel. This bottleneck is the reason why this industry was described as a “geopolitical chess piece” - and is also the cornerstone of the entire AEM investment thesis (as an Intel proxy). So if there’s any part of this Part 1 report you should pay special attention to, it’s this one.
The Fabrication subsector refers to the manufacturing part of the Semiconductor supply chain - i.e. the factory which actually makes the physical chips. In the past, most semiconductor companies tended to be IDMs like Intel today - where they did everything in-house, from the design stage, to the manufacturing stage, the testing stage and finally the sales stage to the end-consumer. However, these days semiconductor companies mostly occupy the aforementioned Chip Design stage alone - these are referred to as “Fab-less companies”. The “fab” in “fabless” refers to the fabrication stage - since these fabless companies typically outsource their manufacturing to pure-play foundries in the Fabrication subsector, e.g. TSMC.
There are several reasons why most semiconductor companies prefer taking the Fabless route. Firstly, starting a foundry typically requires a deca-billion upfront CAPEX commitment - TSMC is committing to spend USD32-36 billion in CAPEX in 2023 alone to prepare for the transition to 3nm transistor density. If you want to know why, it’s because a typical modern semiconductor fab is several soccer fields wide - as evidenced by TSMC’s currently largest operating Fab 18 in the picture below:
Secondly, semconductor fabrication involves an extremely high level of technical competency. Putting aside the logistics of running a gigantic factory, the actual equipment used to manufacture the semiconductor chips are literally more difficult to operate than launching a rocket into outer space. We’ll go into this a little deeper in the Equipment & Software subsector section below - but suffice to say, this business isn’t for the faint of heart.
Thirdly, semiconductor fabrication is a highly commoditized business. Generally, what this means is that there’s very little difference between one business’s product and its competitors - hence the reference to “commodities” (e.g. oil, rice) - and because the products aren’t differentiated, the industry ends up devolving into a price war. In the Fabrication subsector, the product is their ability to manufacture a semiconductor chip, not the final chip itself - and at the highest level, all three competitors (TSMC, Samsung and Intel) can pretty much produce the same chip (this isn’t necessarily true, but let’s just keep things simple for now).
When you put all this together, you’ll recognize how prohibitively high the barriers to entry are to this Fabrication subsector. Even if you had a spare USD100B in capital lying around, you’d still need to have qualified engineers to run the equipment and minimize operational risk - and then you’d still have to compete on price with the existing 3 global players, who by the way have already been doing this for decades. Keep in mind I’m also skipping like 90% of this subsector for the sake of brevity, so the barriers to entry are actually way higher than that. (if you’d like to know more, please feel free to reach out to me in the comments or join our Telegram group)
The reason why I say that this Fabrication subsector is the core of the “geopolitical chess piece” thesis is because as hard as China might try, it is not going to be able to replicate this part of the global semiconductor supply chain on its shores. Not only is there way too much technical and operational complexity involved to do this over a relatively short span of time; but a generous dose of luck is also required to attain the current leading-edge 5nm transistor density manufacturing capacity. I’m going to share a few excellent videos below if you’d like to get up to speed on the history and technical requirements of this Fabrication subsector - but suffice to say this is not an industry you can conjure out of thin air simply by throwing money at the problem.
To be clear, this is only referring to the fabrication of leading-edge semiconductors (e.g. <5nm); and not trailing-edge semiconductors (e.g. >10nm). China is well-equipped to produce trailing-edge semiconductors at scale for use in automobiles, calculators and 5G basestations - but it’s not going to be able to catch up to TSMC, Samsung & Intel and start making 5nm chips for flagship phones with homegrown fabs anytime soon. Keep in mind also that the former 3 companies are not just resting on their laurels - they are also maintaining their current pace in search of ever-increasing transistor densities, which means that China will be chasing constantly moving goalposts.
I’m just going to leave some excellent videos below which provide some insight into the gargantuan technical complexity involved in this Fabrication subsector. In fact, the entire Asianometry Youtube channel where these videos are from is well worth watching, and I’d highly recommending subscribing to it if you want to get up to speed with the increasingly important Semiconductor industry:
And if you thought that the Fabrication subsector was the biggest hurdle China had to overcome in this sector (in the context of geopolitical strategy), you’d have another thing coming. There’s an even bigger hurdle - the Equipment that goes into these fabs to actually make those leading-edge semiconductor chips.
4) Equipment & Software
The fourth stage of the global semiconductor supply chain that comes after the Fabrication subsector is the Equipment & Software subsector. For the purposes of this simplified introduction to the sector, you can basically just pretend that the “Software” part is bundled into the “Equipment” part - so it’s really just about the actual Equipment that is used to make these leading-edge semiconductor chips.
Here, the bottleneck of the sector is even more dramatic - there is only one company in the entire world capable of producing the necessary equipment to manufacture leading-edge semiconductor chips. This company is ASML in the Netherlands, which has a long-term share price that looks like this:
Other than Facebook in the social media sector, I can think of very few companies today that can be credibly considered as global monopolies (keep in mind that Facebook’s future outlook is currently the opposite of ASML’s). There is just nobody else in the present-day who is capable of producing the machines that are used in TSMC’s fabs to manufacture leading-edge semiconductors - which we’ll explore why below.
If you’re familiar with the basics of semiconductor manufacturing, the way to create a semiconductor chip is by etching the transistor design (completed at the Chip Design stage) onto a semiconductor wafer with a laser - after which the wafer is then cut up into separate individual chips. These transistors act like switches when you flow an electrical current through them - where an open/closed switch represents the binary 0’s and 1’s that forms the basis of a computer’s language. Quite apparently, the more transistors you have on a chip, the more switches it has and the more processing power it has - so the trend over time has been to cram more and more transistors onto a single chip (i.e. transistor density). For many reasons, making a semiconductor chip larger to include more transistors involves more tradeoffs than benefits (e.g. heat dissipation) - so higher transistor density has traditionally been the way to go if you wanted to improve chip performance.
As you are familiar with, transistor density is typically described in terms of nanometers (i.e. nm), which is 1 billionth of a meter - or 0.000001 mm. The current generation of leading-edge chips manufactured by TSMC are already approaching 3nm - in comparison, the diameter of a silicon atom is 0.2nm (silicon is the material used to make chips); so there’s a physical limit to how much higher we can make transistor densities. Also, in order to make transistor densities of 3nm, we can’t use traditional lasers anymore to etch the design onto the semiconductor chip - we need to use ASML’s Extreme Ultraviolet Light (EUV) machines as pictured below:
A Quick Note about Transistor Densities (e.g. 3nm):
I want to digress a bit here to provide clarity on what the 3nm transistor density actually means. The “3nm” or “5nm” term that you typically hear being thrown about is actually just a marketing term based on the equivalent ‘nm’ from an older technology that is no longer being used in leading-edge chip manufacturing (i.e. MOSFET). Today’s semiconductor manufacturing uses a newer approach called FINFET - in fact we are already taking the first steps onto the next generation called GAAFET. If you’d like more color on what these acronyms mean, I’d highly recommend watching this 2-minute short video by Samsung:
Also, the same “3nm” term refers to the ‘transistor pitch’ rather than the ‘transistor width’. The former refers to the distance between transistors, while the latter refers to the diameter of the transistor switch itself — and is what is actually relevant with respect to transistor performance (i.e. Moore’s Law). This is because you can only make a transistor width so thin before electrons actually start jumping over the “switch” that the transistor is supposed to function as - and with current methods, layer thickness has already been reduced to just two silicon atoms wide. This is why the industry is currently moving towards increasing transistor densities vertically (e.g. GAAFET) rather than horizontally (e.g. MOSFET), in order to further increase transistor density.
In order to appreciate how mindblowingly complex the inner workings of an EUV machine is, here is how one such machine is used to etch a 5nm design onto a silicon wafer. Firstly, a “regular” laser beam is agitated from neon gas, where it is bounced around on mirrors to “refine” the laser’s “shape”. Halfway through the process, a drop of liquid tin is dripped into an open chamber - whereupon it is hit by the laser in order to absorb its energy and output the extreme ultraviolet light (EUV). Since there is not enough energy in one laser beam to create a usable level of EUV for semiconductor etching, that first laser beam is immediately followed by a second laser beam which hits that same drop of liquid tin - in order to output a sufficiently strong EUV ray.
Think about it, you have to time both pulses of laser to the nanosecond in order to hit a drop of liquid tin even as it is falling down - such that it releases a strong enough EUV ray in that temporarily suspended position. And then you have to do that 4 billion times a day - and hit it just right every single time. The analogy here is to shoot an arrow at an apple located on the moon from Earth - and hit it 4 billion times every single day without fail. Now do you see what I mean when I said earlier that this is more difficult than rocket science?
But wait, there’s more. Now that you’ve created that EUV ray, you need to further “refine” its “shape” using some very special mirrors - since normal mirrors will absorb EUV light. In fact, the next generation of semiconductor manufacturing hinges on this step - where they make the EUV ray even smaller than normal by using a new technique called High-NA EUV (watch the video below for more on this). This EUV ray then hits a photomask which has the finished Chip Design printed on it - and the EUV ray passes through the photomask before finally hitting the semiconductor wafer and etching the transistor design onto it.
In case you have difficulty imagining everything I’ve just said, here’s a helpful video to help you visualize the process:
As you can imagine, the technical complexity required to: hit a falling drop of liquid tin with a laser twice in order to output an EUV ray, which has to be properly shaped by special mirrors before passing through a photomask and etching the final transistor design onto a semiconductor wafer - is completely unfathomable. This is the reason why ASML is currently the only company in the world capable of making these EUV machines - and if you think that’s difficult enough, the next generation of High-NA EUV machines hikes that complexity up by another order of magnitude. You can learn more about the logistics involved in the videos below:
I’m not going to spend anymore time here tunelling down the rabbit hole of High-NA EUV’s technicalities - but I’m sure we can all agree that this is not a problem that you can fix by throwing money at it. And given that ASML is firmly located in the Netherlands (an European country), China is not going to be able to replicate this technology no matter how much money it throws at it or how many talented employees it poaches. It just isn’t technically possible anywhere in the medium-term - we haven’t even talked about the element of luck involved when transitioning from normal EUV to High-NA EUV (which you can learn from the video above).
I’m going to drop a few more videos below which can help you further understand why this Equipment & Software subsector serves as such a strategic bottleneck in the “geopolitical chess piece” narrative:
The point to take home from all this is that since Intel has become the BFF of every Western government in the world and has access to ASML’s High-NA EUV machines, it is very well-positioned to become strategically significant to the US government’s geopolitical objectives - i.e. the Lockheed Martin of Tomorrow.
5) Packaging & Testing
Finally, we come to the youngest child of the global Semiconductor supply chain - the Packaging & Testing subsector. Unlike the previous few subsectors, this subsector is highly fragmented and has thousands of players all around the world.
Perhaps an elaboration of what Packaging & Testing refers to here is in order. “Packaging” refers to the packaging of the semiconductor chip - the chip that you remove from the box isn’t just the chip alone, but is typically the chip packaged into an outer structural shell that helps protect it from structural damage (and supplements some electronic functions). Historically, this subsector was never considered very important by the wider industry - as it merely provided an outer shell to protect the chip and connect it to the rest of the computer, as shown in the picture below:
However, given how we have recently started hitting the physical and engineering limits of cramming more transistors into a chip, increasing focus has been placed on improving the packaging of the chip to get more performance out of it. The analogy to draw here is that since we can’t fit any more toothpaste into the tube, let’s now try to improve the packaging so that we can squeeze more toothpaste out of that same tube.
The recently announced Apple M1 Ultra chip is a prime example of this description being put into practice — where two Apple M1 Max chips (already top-of-the-line RISC chips which can beat most CISC chips in performance) are joined together via a proprietary interconnect solution (the interconnect is part of the packaging). This interconnect solution seems to be an approach which only favors vertically-integrated companies like Apple - as most of its competitors have to support a much more comprehensive range of products. This shows the increasingly important role that the Packaging subsector plays within the wider semiconductor industry in the race for higher performance.
The final subsector is the Testing subsector. As the name implies, this is the part of the supply chain which tests all the completed and packaged chips before they are shipped out for sale to the end-consumer. The purpose of this subsector is to catch faulty chips before they are shipped out — since a faulty chip can have dramatic consequences if placed into a mission-critical product, e.g. an autonomous driving car.
Traditionally, the Testing subsector has also been of relatively lower relevance to the wider Semiconductor industry owing to its ancillary value-add - and as a result this subsector was also highly fragmented. Historically, what companies in this subsector did was some variation of what is referred to by the industry as “functional testing” using Automatic Test Equipment (“ATE”) — which basically just means to test whether the chip is functioning as intended. However, as semiconductor chips are manufactured in higher and higher transistor densities, the complexity of testing them has also ramped up dramatically - and just as we’ve seen with the Packaging subsector earlier, this subsector is also becoming of increasing importance to the wider semiconductor industry. We explore the new-gen successor to ATE in our AEM Holdings (Part 2) stock report.
Check out all of our follow-up Intel articles:
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Thanks for a brilliant read, Aaron!